Storage medium and semiconductor package

ABSTRACT

A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2008-049823, filed on Feb. 29,2008; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a storage medium and a semiconductorpackage.

2. Description of the Related Art

In a storage medium that includes a semiconductor package and a mountingsubstrate on which the semiconductor package is mounted, it has beendesired to further downsize the storage medium with a larger capacity.Conventionally, as one of the methods for realizing downsizing storagemediums with a larger capacity, there has been proposed the use of asemiconductor package of various types such as a ball grid array (BGA)and a land grid array (LGA).

In a BGA semiconductor package or LGA semiconductor package, unlike asemiconductor package of a thin small outline package (TSOP), electrodesare arranged on the bottom surface of a resin encapsulation, and thusthe electrodes (leads) do not extend from the periphery (end surface) ofthe resin encapsulation. At the time of mounting on the mountingsubstrate, the resin encapsulations of the adjacent packages can beplaced close to each other, and this can achieve a high density of asemiconductor chip and downsizing of a storage medium. Conventionally,to achieve a higher density of the semiconductor chip, there has beenalso proposed a semiconductor package of a multi chip package (MCP) inwhich a plurality of semiconductor chips are stacked and encapsulated ina single package.

In such a semiconductor package, while it is possible to achieve a highdensity thereof and downsizing of the storage medium, a large number ofelectrodes are placed on the bottom surface of the resin encapsulation.The large number of electrodes formed on the bottom surface of the resinencapsulation are generally formed in a rectangular grid shape. However,to improve the reliability, the electrodes formed at the corners in thearray are not used for transferring and receiving a signal. This isbecause cracks can be easily generated at the corners of the package(for example, see Japanese Patent Application Laid-open No.2007-207397).

However, a storage medium on which such a semiconductor package ismounted has been desired to have a higher reliability. Recently, astorage medium in which a non-volatile semiconductor memory isincorporated has been used in various areas ranging from large-scalecomputers to personal computers, household appliances, cellular phonesand the like. Further, such a storage medium is even considered as analternative to a hard disk drive (HDD). Therefore, a more reliablestorage medium with excellent impact resistance and temperature cycleresistance has been desired.

BRIEF SUMMARY OF THE INVENTION

A storage medium according to an embodiment of the present inventioncomprises: a semiconductor package having a semiconductor chip, a resinthat encapsulates the semiconductor chip, and a plurality of electrodesarrayed on a bottom surface of the resin; and a substrate including aconductor that joins the electrodes, and having the semiconductorpackage mounted thereon, wherein the electrodes include a signalelectrode formed within a central region of the array, and a dummyelectrode formed outside of the signal electrode.

A semiconductor package according to an embodiment of the presentinvention comprises: a semiconductor chip; a wiring substrate having thesemiconductor chip mounted on a first surface; and a plurality ofprojection electrodes formed on a second surface opposite to the firstsurface of the wiring substrate, wherein a bonding pad to which abonding wire extending from the semiconductor chip is connected isformed at an edge of the first surface on the wiring substrate, and aplurality of projection-electrode forming pads for forming theprojection electrodes are arrayed and formed in a lattice on the secondsurface, and the projection-electrode forming pads for a power supplyline formed within a central region of the array and a pattern extendingto a second surface side on the wiring substrate via a through hole fromthe bonding pad are connected via the projection-electrode forming padsfor a dummy electrode formed within an outer region of the array.

A semiconductor package according to an embodiment of the presentinvention comprises: a semiconductor chip; a wiring substrate having thesemiconductor chip mounted on a first surface; and a plurality ofprojection electrodes formed on a second surface opposite to the firstsurface of the wiring substrate, wherein a bonding pad to which abonding wire extending from the semiconductor chip is connected isformed at an edge of the first surface on the wiring substrate, and aplurality of projection-electrode forming pads for forming theprojection electrodes are formed on the second surface, and a patternextending to the second surface of the wiring substrate via a throughhole from the bonding pad is connected to the projection-electrodeforming pads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a storage medium according to a firstembodiment of the present invention;

FIG. 2 is a cross-sectional view of a part having a semiconductorpackage of an SSD mounted thereon;

FIG. 3 depicts an arrangement of signal electrodes and dummy electrodesof a storage medium according to the first embodiment;

FIG. 4 is an enlarged partial cross-sectional view of a detailedstructure of a semiconductor package;

FIG. 5 depicts connection of bonding wires to semiconductor chips;

FIG. 6 depicts a logarithm graph for comparing a mounting reliability bya temperature cycle test for a BGA semiconductor package and a TSOPsemiconductor package;

FIG. 7 depicts an arrangement of signal electrodes and dummy electrodesof a storage medium according to a second embodiment of the presentinvention;

FIG. 8 depicts an arrangement of signal electrodes and dummy electrodesof a storage medium according to a third embodiment of the presentinvention;

FIG. 9 depicts an arrangement of signal electrodes and dummy electrodesof a storage medium according to a fourth embodiment of the presentinvention;

FIG. 10 depicts a part of a wiring pattern on a second surface of aconventional wiring substrate;

FIG. 11 is a cross-sectional view of a part having a semiconductorpackage according to a fifth embodiment of the present invention mountedthereon;

FIG. 12 depicts wire-bonding of a semiconductor chip to a wiringsubstrate of the fifth embodiment;

FIG. 13 depicts a part of a wiring pattern on a first surface of thewiring substrate of the fifth embodiment;

FIG. 14 depicts a part of a wiring pattern on a second surface of thewiring substrate of the fifth embodiment;

FIG. 15 depicts a pin assignment of solder balls arranged on the secondsurface on the wiring substrate; and

FIG. 16 is an enlarged view of a part of linked pads shown in FIG. 14.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of a storage medium and a semiconductor packageaccording to the present invention will be explained below in detailwith reference to the accompanying drawings. The present invention isnot limited to the embodiments.

FIG. 1 is a perspective view of a storage medium according to a firstembodiment of the present invention. A solid state drive (SSD) 100,which is a storage medium, is a module configured such that a pluralityof semiconductor packages are mounted on a mounting substrate(motherboard) 30, which is a small rectangular substrate of 3millimeters (mm) in thickness. The semiconductor packages are BGAsemiconductor packages in which each semiconductor chip is encapsulatedwith a resin. Each semiconductor package includes eight semiconductorpackages 40 each incorporating a NAND flash memory as a non-volatilememory, a semiconductor package 50 incorporating a drive control circuitas a controller, a semiconductor package 60 incorporating a DRAM as avolatile memory, and a semiconductor package 70 incorporating a powersupply circuit. Furthermore, a connector 80 is arranged on one of theshort sides of the outer periphery of the mounting substrate 30.

The outer dimension of the mounting substrate 30 is substantially thesame in size as that of a 1.8-inch HDD, according to the HDD standard.The connector 80 is also fabricated based on the HDD standard, and ahigh-speed serial ATA that is the same as the HDD is adopted for aninterface. The semiconductor package 40 incorporating the NAND flashmemory is 14×18 mm in outer dimension, and is a maximum of 1.46millimeters in height from the mounting substrate 30. This height islower than 2.35 millimeters, that is, a height obtained by superposingtwo TSOP semiconductor packages incorporating four semiconductor chips(that is, a height when semiconductor chips having thereon with eightchips are realized by the TSOP semiconductor package) (according to thecurrent limitation, only up to four semiconductor chips can beencapsulated with a resin in the TSOP semiconductor package).

FIG. 2 is a cross-sectional view of a part having the semiconductorpackage 40 incorporating the NAND flash memory of the SSD 100 shown inFIG. 1 mounted thereon. The semiconductor package 40 is configured byeight semiconductor chips 5 each formed with a NAND flash memory, aresin encapsulation 10, in an approximate flat-plate shape, thatencapsulates the semiconductor chips 5 with a resin, and solder balls20, as lattice electrodes, formed to be arrayed in a lattice (gridshape) on the bottom surface of the resin encapsulation 10. Amultiple-valued technology for recording any one of values “00”, “01”,“10”, and “11” for each memory cell is adopted in the NAND flash memory,and a capacity per device is further improved as compared to that of adouble-valued technology. A NAND flash memory that can store up to 2gigabytes is formed in each semiconductor chip 5, and 128 gigabytes canbe stored in the entire SSD 100. The number of semiconductor chips isnot limited to eight, and is changed appropriately depending on acapacity of the storage medium or the like.

The resin encapsulation 10 includes a wiring substrate (interposer) 7,an encapsulation resin 8, and a bonding wire 9. On the wiring substrate7, the semiconductor chips 5 are mounted on a first surface (topsurface), and the solder balls 20 are formed on a second surface(reverse surface) that faces the first surface. The encapsulation resin8 encapsulates the eight semiconductor chips 5 with a resin on the firstsurface side of the wiring substrate 7. The bonding wire 9 electricallyconnects the semiconductor chip 5 and the wiring substrate 7. The solderballs 20 are soldered and joined to a joining conductor 31 that isformed as a wiring pattern on the mounting substrate 30.

FIG. 3 depicts how the solder balls 20 are arrayed to form a linelengthwise and crosswise, and also depicts the semiconductor package 40as seen from the second surface side of the wiring substrate 7. Thesolder balls 20 are formed to be aligned lengthwise and crosswise on thesecond surface of the wiring substrate 7. In the array of the solderballs 20, there is a basic part (part surrounded by a long dash shortdash line in FIG. 3) that is so arrayed in an approximate rectangularshape that its center matches that of the wiring substrate 7. In thebasic part, about 16 solder balls form a line in the long-side directionof the wiring substrate 7 while about 12 solder balls form a line in theshort-side direction thereof. Further, at the four corners of the array,additional one or two lines of solder balls 20 are formed on theoutside. The solder balls 20 are not arranged in a region worth 2×6balls (part surrounded by a long dashed double short dashed line) at thecenter of the wiring substrate 7 of the array.

The solder balls 20 thus formed are divided into signal electrodes 20Aindicated by black circles in FIG. 3 and formed within a predeterminedregion at the center of the array indicated by the dashed line(hereinafter, “central region”), and dummy electrodes 20B indicated bywhite circles and formed on the outside of the signal electrodes 20A.The central region in which the signal electrodes 20A are formed is aregion having a width about ⅓ the entire width in the long-sidedirection of the array. The signal electrodes 20A are formed and mixedwith the dummy electrodes 20B in the central region. On the other hand,some of the dummy electrodes 20B are formed and mixed with the signalelectrodes 20A in the central region, as described above. The remainingdummy electrodes spread out in the both-side direction of the centralregion, and in this area, only the dummy electrodes 20B are formed in anarray to occupy the remaining region on the wiring substrate.

The signal electrodes 20A are used for transferring and receiving asignal, and function as data pins, command pins, power supply pins (suchas grounding and Vdd), and clock pins, for example. Meanwhile, the dummyelectrodes 20B are not used for transferring and receiving a signal, butare used for fixedly supporting the semiconductor package 40. In thiscase, 224 solder balls 20 are formed, for example. Among those, thereare 30 signal electrodes 20A and 194 dummy electrodes 20B. That is, theratio in number between the signal electrodes 20A and the dummyelectrodes 20B is about 2:13, and the proportion of the number of signalelectrodes 20A to the entire region is about 13%.

The impact resistance and temperature resistance tests performed by theinventors found out that in joining parts of the lattice electrodesjoined to the mounting substrate through soldering or the like, cracksare generated due to external stress such as impacts, and also due tosolder fatigue caused by a temperature cycle, from a jointing part witha larger distance from the center, that is, from a joining partpositioned on the outer side of the array. The tests also showed thatthere was a tendency that these cracks moved gradually towards the innerside. Accordingly, in the first embodiment, the signal electrodes 20Aare formed on the center side of the lattice array and the dummyelectrodes 20B are formed on the outside of the array. This lengthensthe time taken until cracks are generated in the signal electrodes 20A,thereby improving the impact resistance and temperature cycleresistance. Furthermore, the cracks tend to appear first at the fourcorners of the array, that is, the position with a large distance fromthe center. Therefore, in the first embodiment, the additional one ortwo lines of the dummy electrodes 20B are further formed on the outsideof the array at the four corners in the array. As a result, theadhesiveness at the corners can be enhanced, thereby leading to furtherimprovement in the impact resistance and temperature cycle resistance.

To achieve the effects described above, it is effective to sufficientlyincrease the number of the dummy electrodes 20B placed around the signalelectrodes 20A as compared to the number of signal electrodes 20A. Basedon this, as in the first embodiment, when the number of the signalelectrodes 20A was set to around 30 out of the total of 224 electrodes(about 13%), it was possible to achieve favorable effects such as theimpact resistance and temperature cycle resistance.

With respect to the proportion of the signal electrodes 20A to all theelectrodes, when the inventors adjusted the number of the signalelectrodes in a semiconductor package of 14×18 mm similar to that of thefirst embodiment, a major effect was gradually achieved as the signalelectrodes were reduced until the proportion of the number to the signalelectrodes was made to about 10% (for example, 22 electrodes out of 224electrodes). However, even when the number of signal electrodes wasfurther reduced, there was no remarkable increase in the effect. Whenthe same tests were performed for a semiconductor package of a differentsize in addition to the semiconductor package of 14×18 mm, it was foundthat the same effect was achieved with an approximately identical ratio.

The solder balls 20 do not necessarily have to be formed in alignment ina lattice at an equal pitch lengthwise and crosswise. The solder balls20 can also be irregularly formed in groups (electrodes in a group)rather than at an equal pitch. Further, with respect to the outerperipheral shape of the group, not only square but also trapezoid, ovalor the like can be adopted. That is, from among the solder balls formingthe group, the signal electrodes are formed within a predeterminedregion of the center of the group and the dummy electrodes are formed onthe outside of the signal electrodes, and therefore the effectsubstantially identical to that described above can be achieved.

A more detailed configuration of the first embodiment is explained. FIG.4 is an enlarged partial cross-sectional view of a detailed structure ofthe semiconductor package 40. Specifically, the wiring substrate 7 isformed with a copper wiring pattern 13 on the surface of a core material11 made of a resin material. The wiring substrate 7 is so fabricatedthat a copper foil is pasted on the plate-shaped core material 11, thesurface is etched, for example, to form the copper wiring pattern 13,and the surface is coated with a solder resist 15 for the purposes ofpreventing oxidation to maintain insulation. A through hole not shown isformed in the core material 11 in a manner to match the array of thesolder balls 20, and the wiring pattern 13 is so formed that itpenetrates the through hole to be exposed on the second surface side ofthe wiring substrate 7. The solder balls 20 are formed on the wiringpattern 13 exposed from the core material 11, via an electrolyticplating 17 of either nickel or aluminum.

The eight semiconductor chips 5 are stacked by being fixed with a dieattaching film 19 with one another. The die attaching film 19 is mixedwith epoxy and polyamide, and serves as an adhesive agent. The bondingwires 9 extending from the semiconductor chips 5 are connected to thewiring pattern 13 at the end of the wiring substrate 7. To enable aneasy connection of the bonding wires 9, the eight semiconductor chips 5are stacked in a slightly deviating manner. That is, the semiconductorchips 5 on the upper side are stacked to be deviated by a predeterminedamount to a side that faces the bonding wires 9 so that the othersemiconductor chips 5 overlapped on the upper side are not overlapped onthe top surface of the periphery to which the bonding wires 9 areconnected. The semiconductor chips 5 are bonded with wiring for everytwo stacked semiconductor chips 5, and this pattern is repeated fourtimes to stack the eight semiconductor chips. Thereafter, theencapsulation resin 8 is molded by a metal mold to cover thesemiconductor chips 5 and the bonding wires 9.

FIG. 5 depicts connection of the bonding wires 9 to the semiconductorchips 5, and also depicts a state that the encapsulation resin 8 isremoved as seen from an arrow a side of FIG. 2. The bonding wires 9 areconnected to one side of each semiconductor chip 5. As understood incombination of FIG. 2, two semiconductor chips 5 adjacent in thestacking direction form a set, and the bonding wires 9 extending fromeach set are separately connected at four different locations so as notto overlap one another in the stacking direction of the semiconductorchip 5. When the semiconductor chips 5 are stacked and bonded asdescribed above, facilitating a work process and downsizing of thesemiconductor package can be achieved.

The SSD 100 configured as above is mounted with the semiconductorpackage 40 including the semiconductor chips 5 formed with anon-volatile semiconductor memory constituted by a NAND flash memory,the resin encapsulation 10 that encapsulates the semiconductor chips,and the solder balls 20 formed to be arrayed in a lattice on the bottomsurface of the resin encapsulation 10. In such a type of a semiconductorpackage, the electrodes (leads) do not extend in the direction along themounting substrate 30 from the periphery (end surface) of the resinencapsulation 10, unlike in a TSOP semiconductor package. Therefore, atthe time of mounting on the mounting substrate 30, the resinencapsulation 10 of the adjacent packages can be placed densely.Accordingly, the proportion of the area of the resin encapsulation 10 tothe mounting substrate 30 can be increased, and consequently, a highdensity of semiconductor chips can be implemented. Further, in the firstembodiment, the eight semiconductor chips are mounted in the singlesemiconductor package 40, and therefore the high density can be furtherimproved. Further, the semiconductor package 40 is a BGA package, anddoes not use a lead frame at the time of forming the resin encapsulation10. Thus, the thickness of the semiconductor package 40 can be reduced.

Further, the solder balls 20 of the SSD 100 according to the firstembodiment include the signal electrodes 20A formed at the center of thelattice array (within a region about ⅓ the central part, in thelong-side direction), and the dummy electrodes 20B formed outside ofthis region. Accordingly, the impact resistance and the temperaturecycle resistance can be promoted, which leads to an improvement in thereliability of the SSD 100. The semiconductor package 40 has 224 solderballs 20 including a large number of the dummy electrodes 20B, and thisnumber is far greater than the number of electrodes (leads), i.e., 46,of a TSOP package of the same size. Therefore, the heat generated in thesemiconductor chips 5 can be favorably conducted to the mountingsubstrate 30 via the solder balls 20, and a favorable radiation effectis achieved as a result.

FIG. 6 depicts a logarithm graph for comparing a mounting reliability bya temperature cycle test for the BGA semiconductor package 40 used inthe SSD 100 and a TSOP semiconductor package conventionally used. In thetemperature cycle test, the temperature of the package was fluctuatedbetween −25° C. and 125° C. at an interval of 30 minutes, and cumulativedefect rates at that time were measured for comparison. A horizontalaxis represents the number of cycles [number of times] while a verticalaxis represents a cumulative defect rate [%]. In FIG. 6, triangular plotmarks represent the number of cycles when a predetermined cumulativedefect rate is reached in the TSOP package, while black circular plotmarks represent the number of cycles when a predetermined cumulativedefect rate is reached in the BGA package. For example, when comparingthe numbers of cycles at which the cumulative defect rate of 1% isattained, this defect rate is attained at a cycle of 467 times in theTSOP semiconductor package while this defect rate is attained at a cycleof 900 times in the BGA semiconductor package 40. From this, it wasdemonstrated that the semiconductor package 40 according to the firstembodiment had an operating life increased by about 1.93 times.

In the first embodiment, in the semiconductor package 70 incorporatingsemiconductor parts, such as a power supply circuit placed at theperiphery of the mounting substrate 30, it is effective to fill anunderfill agent (resin sealant) between the resin encapsulation 10 andthe mounting substrate 30 so that the solder balls 20 are encapsulated,to improve the impact resistance and the temperature cycle resistance.With this configuration, the adhesiveness between the resinencapsulation 10 and the mounting substrate 30 is increased. Inaddition, the solder balls 20 are protected from the external stress,and as a result, the generation of cracks is further suppressed, therebyfurther improving the reliability of the SSD.

Meanwhile, out of the semiconductor packages 40, 50, and 60, withrespect to the semiconductor packages 40 being placed densely to oneanother on the mounting substrate 30 and incorporating the NAND flashmemory, it is effective to increase the number of dummy electrodes atthe corners for reinforcement as described above, rather than using theunderfill agent.

FIG. 7 depicts an arrangement of signal electrodes and dummy electrodesof a storage medium according to a second embodiment of the presentinvention. Solder balls 120 according to the second embodiment can bedivided into signal electrodes 120A indicated by black circles in FIG. 7and formed at the center of a lattice array, and dummy electrodes 120Bindicated by white circles and formed on the outside of the array. Alsoin the second embodiment, there are 224 solder balls 120, and out ofthese, there are 30 signal electrodes 120A while there are 194 dummyelectrodes 120B. The signal electrodes 120A are formed within a regionabout ⅓ the central part in the both long-side direction and theshort-side direction of the array.

The signal electrodes 120A according to the second embodiment are placedto exhibit line symmetry about a center line L on a plane of a secondsurface of the wiring substrate 7. When the signal electrodes 120A areplaced to exhibit line symmetry about the center line, it becomespossible to eliminate the case that the cracks generate easily on anyone half, that is, if there are cracks, they will be generated evenly.Therefore, the impact resistance and the temperature cycle resistancecan be further improved. Furthermore, as described in the secondembodiment, when the dummy electrodes 120B are placed in a manner toenclose the signal electrodes 120A across the entire circumference, theeffect can be further increased.

FIG. 8 depicts an arrangement of signal electrodes and dummy electrodesof a storage medium according to a third embodiment of the presentinvention. Solder balls 220 according to the third embodiment can bedivided into signal electrodes 220A indicated by black circles in FIG. 8and formed at the center of a lattice array and dummy electrodes 220Bindicated by white circles formed on the outside of the array. Also inthe third embodiment, there are 224 solder balls 220, and out of these,there are 30 signal electrodes 220A while there are 194 dummy electrodes220B. The signal electrodes 220A are formed within a region in anapproximate square obtained by rotating by 45° at the central partrelative to the array of which the entire shape is rectangular.

The signal electrodes 220A are placed to exhibit point symmetry about acenter point P on a plane of a second surface of the wiring substrate 7.When the signal electrodes 220A are placed to exhibit point symmetryabout the center, it becomes possible to eliminate the case that thecracks are easily generated on any one half. Therefore, effectssubstantially identical to those in the second embodiment can beachieved. As described in the third embodiment, when a region in whichthe signal electrodes 220A are formed is a region in an approximatesquare obtained by rotating by 45° at the central part, the signalelectrodes 220A can be placed at the farthest location from the cornerswhere the cracks can be generated easily. This is effective to improvethe impact resistance and the temperature cycle resistance.

FIG. 9 depicts an arrangement of signal electrodes and dummy electrodesof a storage medium according to a fourth embodiment of the presentinvention. Solder balls 320 according to the fourth embodiment can bedivided into signal electrodes 320A indicated by black circles in FIG. 9and formed at the center of a lattice array and dummy electrodes 320Bindicated by white circles and formed on the outside of the array. Alsoin the fourth embodiment, there are 224 solder balls 320, and out ofthese, there are 48 signal electrodes 320A while there are 176 dummyelectrodes 320B. That is, the number of the signal electrodes 320A isincreased as compared to that in the first to third embodiments. Thecentral region in which the signal electrodes 320A are formed is aregion having a width about ½ the entire width of the array.

In the near future, it is expected that in the semiconductor package,the number of signal electrodes is increased to correspond to the factthat the semiconductor chips are further multilayered, for example.However, as described in the first embodiment, when achieving the effectof the impact resistance and the temperature cycle resistance providedby the dummy electrodes, it is not effective to reduce the number ofpins of the dummy electrodes surrounding the signal electrodes beyondthe required number relative to the signal electrodes. However, asdescribed in the fourth embodiment, out of a total of 224 electrodes,when the number of the signal electrodes 320A is 48 (about 21% of thetotal number) and when the central region in which the signal electrodes320A are formed is a region having a width about ½ the entire width ofthe array, a favorable effect is achieved.

When the inventors repeated tests while increasing the proportion of thesignal electrodes, it was possible to improve the impact resistance andtemperature cycle resistance until the number of signal electrodes wasreduced to 66 (about 30%). However, when the number was furtherincreased, there was no significant improvement in the impact resistanceand temperature cycle resistance. Furthermore, when the central regionin which the signal electrodes are formed was changed to a region havinga width equal to or more than ½ the entire width of the array, theeffect deteriorated significantly. As a result, in view of these testresults of the first embodiment, it was found out that the appropriateregion in which the signal electrodes are formed was a region having awidth in a range of about ⅓ to ½ the entire width. For example, theappropriate examples include 5.6/14.4≈⅓ (the example shown in FIG. 3),and 7.2/14.4≈½ (the example shown in FIG. 9). It was also found out thatit is appropriate to set the proportion of the signal electrodes to theentire electrodes is less than 30%, and desirably, the proportion wasless than 20%. It was also found out that when the proportion of thesignal electrodes was equal to or more than 10% and less than 30%, theeffect was achieved effectively. Note that it has become known from thetest that the relationship between the ratio of the signal electrodesand the effect is not limited to a semiconductor package of 14×18 mm,and a substantially identical result was obtained in semiconductorpackages of other sizes as well.

In the SSD of the first to fourth embodiments, the BGA semiconductorpackage is adopted for the purposes of achieving a high density of thesemiconductor chips. However, to achieve the same purpose, not only asemiconductor package of BGA but also that of LGA can be used. In theLGA semiconductor package, instead of the solder balls, very small andflat electrodes in a lattice, which are called “land”, are formed on thebottom surface of the resin encapsulation. The rest of the configurationof the LGA semiconductor package is similar to that of the BGAsemiconductor package. These electrodes are forced into a socket shapedlike a pin support (pin holder) in which pins corresponding to therespective electrodes form a line in a lattice, and attached to themounting substrate.

According to the tests conducted by the inventors, also in the LGAsemiconductor package, starting from a joint that is farthest from thecenter, defective joining is generated at the joints of the latticeelectrodes due to external stress, such as impacts. The defectivejoining gradually moves towards the inner-side electrodes with thepassage of time. Thus, also in the LGA semiconductor package, the signalelectrodes and the dummy electrodes are placed based on the same conceptas in the first to fourth embodiments, and therefore the durabilityagainst external stress can be improved.

Further, according to the inventors, not only in the BGA or LGAsemiconductor packages, but also in any type of semiconductor packagehaving a plurality of electrodes formed in an array on the bottomsurface of the resin encapsulation, the defective joining is generatedat the joints due to external stress, such as impacts, starting from thejoint that is farthest from the center. Therefore, when signalelectrodes and dummy electrodes are formed based on the same concept asin the first to fourth embodiments, the durability against externalstress can be improved.

An object of a fifth embodiment of the present invention is explained bydescribing a configuration of a wiring substrate of a conventionalsemiconductor package that corresponds to a semiconductor packageaccording to the fifth embodiment. FIG. 10 depicts a part of a wiringpattern formed on a second surface (a surface on which solder balls areformed) of a wiring substrate 107 of the conventional semiconductorpackage having a structure similar to that of the semiconductor packageaccording to the fifth embodiment. The wiring pattern is configured toinclude solder-ball (projection-electrode) forming pads (hereinafter,“pads”) 21 for forming solder balls (projection electrodes), on itssurface. The pads 21 are arrayed and formed in a lattice to set to thepositions of the solder balls.

The surface of respective pad 21 is plated so that the solder balls canbe formed easily. At the time of plating the pads 21 at a step ofmanufacturing a semiconductor package, the plating is performed whilerespective pad 21 is applied voltage. A plating process electrode 33 forapplying voltage to respective pad 21 is placed at the edge of thewiring substrate 107 at the time of the plating process (FIG. 10). Thus,patterns for supplying plating process power to respective pad 21 fromthe plating process electrode 33 (hereinafter, “plating lines 22”) arepreviously arranged in an extending manner to reach the edge of thewiring substrate 107 from respective pad 21.

Although not shown, the edge of a first surface (surface on which thesemiconductor chips are formed) opposite to the wiring substrate 107 isformed with bonding pads (bonding fingers). The bonding wires extendingas signal lines or power supply lines from the semiconductor chips areconnected to the bonding pads. The pads 21 for a signal line or a powersupply line, out of a plurality of pads 21 formed on the second surface,are electrically connected to these bonding pads via through holes 23 bya predetermined pattern. Thus, the pads 21 for a signal line or a powersupply line can utilize the pattern at the time of the plating processto apply the voltage. As a result, the plating lines are not needed. Theplating lines are needed by the pads 21 for a dummy electrode notconnected to the bonding pads. On the wiring substrate 107, dummypatterns 24 in a round small circle for burying vacant regions on thesubstrate to prevent the warping of the substrate, for example, are alsoformed.

A large number of dummy electrodes exist in the outer region of thearray, similarly to those in the first to fourth embodiments. Thus, theplating lines 22 extending from respective pad 21 for a dummy electrodeoccupy a large area on the substrate surface (FIG. 10). As a result,there is a case that the degree of freedom of a pattern layout for asignal line or a power supply line, of which the roles are inherentlyimportant, deteriorates, and another case is that because there are avery large number of plating lines 22, the pattern becomes complicated,resulting in a factor for a cost increase, and thus the improvement isdesired. Further, due to the influence that an allowable width of areference voltage of the recent semiconductor chips is narrowed, thereis a demand that the power supply applied to the semiconductor chip ismore stabled. To supply the power supply stably, it is desired that thepattern for a power supply line is laid out as linearly as possible andalso the pattern course is as short as possible. However, due to theexistence of the plating lines 22, it is difficult to set the desiredcourse, and thus the improvement is desired. The fifth embodiment isintended to solve such problems, and is described below.

FIG. 11 is a cross-sectional view of how the semiconductor chips 5 ofthe semiconductor package 41 according to the fifth embodiment arestacked. The semiconductor package 41 is configured by the eightsemiconductor chips 5, the resin encapsulation 10 that encapsulates thesemiconductor chips 5 with a resin, and the solder balls 20 formed andarrayed in a lattice on the bottom surface of the resin encapsulation10. The resin encapsulation 10 includes the wiring substrate 7, theencapsulation resin 8, and the bonding wire 9. On the wiring substrate7, the semiconductor chips 5 are mounted on a first surface, and thesolder balls 20 are formed on a second surface that faces the firstsurface. The bonding wires 9 electrically connect chip pads 26 arrangedat edges alternately different to one another on the stackedsemiconductor chips 5 and a bonding pad 27 arranged at the edge of thewiring substrate 7. The solder balls 20 are electrically connected tothe bonding pad 27 by patterns formed on the first surface and thesecond surface on the wiring substrate 7. The pattern formed on thefirst surface and the pattern formed on the second surface are connectedby the through hole 23. On the semiconductor chips 5, a non-volatilesemiconductor memory constituted by a NAND flash memory is formedsimilarly to those in the first to fourth embodiments.

FIG. 12 depicts wire-bonding of the semiconductor chip 5 to the wiringsubstrate 7, and also depicts a state that the encapsulation resin 8 isremoved as seen from an arrow B side in FIG. 11. The bonding pads 27according to the fifth embodiment are arranged at edges of two shortsides on the rectangular wiring substrate 7, differently from thebonding pads according to the first to fourth embodiments. The bondingwires 9 extending from the chip pad 26 of the semiconductor chip 5 areconnected to the bonding pads 27. Thus, the bonding pads 27 are arrangedon the two short sides on the wiring substrate 7. As a result, thedistance to the central region of the substrate is longer. Accordingly,in the pattern for a power supply line, an improved linearity isrequired.

FIG. 13 depicts a part of the wiring pattern formed on the first surfaceon the wiring substrate 7 according to the fifth embodiment. FIG. 14depicts a part of the wiring pattern similarly formed on the secondsurface of the wiring substrate 7. In FIGS. 13 and 14, the dummy patternand the like for preventing the warping of the wiring substrate 7 areomitted. On the first surface on the wiring substrate 7 shown in FIG.13, the bonding pads 27 arranged on the short side on the wiringsubstrate 7 and predetermined through holes 23 are connected bypatterns. On the other hand, on the second surface side on the wiringsubstrate 7 shown in FIG. 14, a plurality of pads 21 including pads fora signal line or a power supply are formed in an array in the centralregion (within a long dash short dash line frame in FIG. 14) of thearray. In the outer region thereof, the pads 21 for a dummy electrodeare formed in an array. The through holes 23 and the predetermined pads21 are connected by patterns. As described above, an electric route fromthe semiconductor chip 5 through the bonding wires 9 to the bonding pads27 is drawn by a predetermined pattern on the first surface on thewiring substrate 7, and thereafter, reaches the second surface side viathe through holes 23, and extends to the pads 21 for a signal line or apower supply line formed in the central region.

In this case, on the second surface side on the wiring substrate 7 shownin FIG. 14, the pattern for a signal line, for example, extends via thethrough hole 23 (23s) to one pad 21 (21s) for a signal line within thecentral region. On the other hand, the pattern for a power supplyextends from the through hole 23 (23a) over a plurality of pads 21 for adummy electrode to the pad 21 (21g) for a power supply line within thecentral region.

The pattern for a power supply is described further in detail. FIG. 15depicts a pin assignment of the solder balls arranged on the secondsurface on the wiring substrate 7. In FIG. 15, in the central region(within a bold-lined frame in FIG. 15) of the array, a plurality ofelectrodes including electrodes for a signal line and a data line(hatched region without characters in FIG. 15) or a power supply line(Vcc and Vss in FIG. 15) are formed in an array. On the other hand, inthe outer region (outside the bold-lined frame in FIG. 15), a pluralityof electrodes including the dummy electrode ((Vcc), (Vss), and NU inFIG. 15) are formed in an array. In the pin assignment in FIG. 15, sevenVccs (four Vccs forming a line in the right and left directions in theouter region in FIG. 15 and three Vccs forming a line in an L-lettershape within the central region) in a part indicated by E in FIG. 15,for example, are electrically connected to one another. A wiring patternconnecting this part is seven pads indicated by D in FIG. 14. Anenlarged part D in FIG. 14 is shown in FIG. 16. In FIG. 16, the sevenpads (pads 21a to 21g) starting from the through hole 23 (23a)electrically connect the seven Vccs in the part indicated by E in FIG.15. These pads (pads 21a to 21g) are connected to the bonding pad 27(FIG. 13) via the through hole 23 (23a).

As described above, the seven Vccs in the part indicated by E in FIG. 15are connected to one another, and from any one of the pads 21a to 21g, apower supply is enabled. However, in an actual product, the power issupplied from the solder balls (three Vccs forming a line in an L-lettershape within the central region) formed on the pads 21e to 21g. Thereason for this is to improve the reliability for the impact resistanceand temperature cycle resistance, as described in the first to fourthembodiments. By a similar configuration, the respective pad in a groupof Vccs (Vccs) and a group of Vss's (Vss's) shown in the pin assignmentin FIG. 15 is electrically connected to each other. A plurality of NUslocated at the corners of the pin assignment in FIG. 15 are electricallyconnected to one another by a plurality of linked pads, and the linkedpads are further connected with one plating line extending to the edgeon the wiring substrate.

A plurality of pads 21 adjacent in this way are linked by the shortpattern, and further, the groups of linked pads are electricallyconnected to the bonding pads 27. Therefore, a plurality of connectedpads 21 for a dummy electrode become able to supply power from thebonding pads 27 at the time of plating, and thus the plating line is notneeded. As a result, the number of plating liens is greatly reduced, andthus the pattern layout becomes easy. Accordingly, the pattern for apower supply line can be made linear with the shortest course.

The present invention is not limited to the above embodiments, and canbe embodied by modifying constituent elements without departing from thescope of the invention. Furthermore, various inventions can be createdby combinations of the constituent elements disclosed in the aboveembodiments. For example, some of the whole constituent elementsdisclosed in the embodiments can be omitted, and the constituentelements according to different embodiments can be suitably combinedwith each other.

What is claimed is:
 1. A storage medium comprising: a semiconductorpackage having a semiconductor chip, a resin encapsulation thatencapsulates the semiconductor chip, and a plurality of electrodesarrayed on a bottom surface of the resin encapsulation; and a substrateincluding a conductor that joins the electrodes, and having thesemiconductor package mounted thereon, wherein the electrodes include aplurality of signal electrodes formed within a central region of thearray, and a plurality of dummy electrodes formed in an outer region ofthe signal electrodes, each of the signal electrodes includes a firstpad as a projection-electrode forming pad for a power supply line or asignal line, and a first projection electrode formed on the first pad,and each of the dummy electrodes includes a second pad as aprojection-electrode forming pad for a dummy electrode and a secondprojection electrode formed on the second pad.
 2. The storage mediumaccording to claim 1, wherein only the dummy electrodes among the signalelectrodes and the dummy electrodes are disposed in the outer region. 3.The storage medium according to claim 1, wherein the dummy electrodefurther includes a third pad for burying a vacant region, and noprojection electrode is formed on the third pad.
 4. The storage mediumaccording to claim 1, wherein the central region in which the signalelectrodes are formed has a region of a width about ⅓ to ½ of entirewidth of the array.
 5. The storage medium according to claim 1, whereina proportion in number of the signal electrodes to the electrodes isless than 30%.
 6. The storage medium according to claim 1, wherein aproportion in number of the signal electrodes to the electrodes is lessthan 20%.
 7. The storage medium according to claim 1, wherein the signalelectrodes are placed to exhibit line symmetry about a center line ofthe array formed by the electrodes or point symmetry about a center ofthe array.
 8. The storage medium according to claim 1, wherein the dummyelectrodes are formed to enclose entire circumference of the signalelectrodes.
 9. The storage medium according to claim 1, whereinsemiconductor chips are stacked and encapsulated in the resinencapsulation.
 10. The storage medium according to claim 1, wherein thesemiconductor chip has a NAND flash memory incorporated therein.
 11. Asemiconductor package comprising: a semiconductor chip; a wiringsubstrate having the semiconductor chip mounted on a first surface; anda plurality of projection electrodes formed on a second surface oppositeto the first surface of the wiring substrate, wherein a bonding pad, towhich a bonding wire extending from the semiconductor chip is connected,is formed at an edge of the first surface on the wiring substrate, and aplurality of projection-electrode forming pads for forming theprojection electrodes are arrayed and formed in a lattice on the secondsurface, and the projection-electrode forming pads include firstprojection-electrode forming pads as projection-electrode forming padsfor a power supply line formed within a central region of the array andsecond projection-electrode forming pads as projection-electrode formingpads for a dummy electrode formed in an outer region of the centralregion, the projection electrodes include first projection electrodesformed on the first projection-electrode forming pads and secondprojection electrodes formed on the second projection-electrode formingpads, two or more second projection-electrode forming pads among thesecond projection-electrode forming pads are connected to one another bya connection pattern formed on the second surface, and the firstprojection-electrode forming pads are connected to the bonding padthrough the plurality of second projection-electrode forming padsconnected by the connection pattern, and a through hole formed in thewiring substrate.
 12. The semiconductor package according to claim 11,wherein in the second projection-electrode forming pads connected by theconnection pattern, the second projection-electrode forming padsadjacent to each other are connected.
 13. The semiconductor packageaccording to claim 11, wherein only the second projection-electrodeforming pads are disposed in the outer region.
 14. The semiconductorpackage according to claim 11, wherein the wiring substrate forms arectangle, and the bonding pad is arranged at an edge on a short side ofthe wiring substrate.
 15. The semiconductor package according to claim11, wherein the semiconductor chips are stacked and mounted on thewiring substrate.
 16. A storage device comprising: a semiconductorpackage including a plurality of semiconductor chips, a substrate, aresin encapsulation that encapsulates the plurality of semiconductorchips, and an array of electrodes on a bottom surface of the substrate,the plurality of semiconductor chips being mounted on the substrate;wherein the electrodes include a plurality of signal electrodes formedwithin a central region of the array, a plurality of dummy electrodesformed on an outer region outside of the central region, and aproportion of a number of the signal electrodes to a total number of theelectrodes is 10-30%, the signal electrodes include a first pad as aprojection-electrode forming pad for a power supply line or a signalline, and a first projection electrode formed on the first pad, and thedummy electrodes include a second pad as a projection-electrode formingpad for a dummy electrode and a second projection electrode formed onthe second pad.
 17. The storage device according to claim 16, whereinthe outer region includes a first region and a second region, the firstregion including the dummy electrodes surrounding the central region andincluding four corners, the second region including one or more lines ofthe dummy electrodes formed outside of the four corners of the firstregion.
 18. The storage device according to claim 16, wherein only thedummy electrodes among the signal electrodes and the dummy electrodesare disposed in the outer region.
 19. The storage device according toclaim 16, wherein at least one of the dummy electrodes further includesa third pad for burying a vacant region, and no projection electrode isformed on the third pad.
 20. The storage device according to claim 16,wherein the central region in which the signal electrodes are formed hasa region of a width about ⅓ to ½ of an entire width of the array. 21.The storage device according to claim 16, wherein a proportion in numberof the signal electrodes to the electrodes is less than 20%.
 22. Thestorage device according to claim 16, wherein the signal electrodes areplaced to exhibit line symmetry about a center line of the array formedby the electrodes or point symmetry about a center of the array.
 23. Thestorage device according to claim 16, wherein the dummy electrodes areformed to enclose an entire circumference of the signal electrodes. 24.The storage device according to claim 16, wherein the semiconductorchips are stacked and encapsulated in the resin encapsulation.
 25. Thestorage device according to claim 24, the substrate comprises a wiringsubstrate, wherein the wiring substrate and a plurality of bonding wiresare encapsulated in the resin encapsulation, the bonding wires areelectrically connected to the semiconductor chips and the wiringsubstrate, the bonding wires extending from the semiconductor chips areconnected to a wiring pattern at an end of the wiring substrate, and thesemiconductor chips are stacked in a slightly deviating manner in theresin encapsulation.
 26. The storage device according to claim 25,wherein the semiconductor chips are stacked to be deviated by apredetermined amount such that top surfaces of peripheries of thesemiconductor chips to which the bonding wires are connected are notoverlapped by another one of the semiconductor chips, and one of thebonding wires is connected to one side of each of the semiconductorchips.
 27. The storage device according to claim 25, wherein theelectrodes form a line in a long-side direction of the array and a linein a short-side direction of the array, and the electrodes are arrayedin an approximate rectangular shape that has a center matching that ofthe wiring substrate.
 28. The storage device according to claim 25,further comprising: bonding pads arranged on a short side of the wiringsubstrate, and through holes in the wiring substrate are connected bypatterns on the wiring substrate.
 29. The storage device according toclaim 25, wherein the first pads are electrically connected to at leastone of the semiconductor chips by a through hole and a pattern on thewiring substrate.
 30. The storage device according to claim 16, whereinat least one of the semiconductor chips has a NAND flash memoryincorporated therein.
 31. The storage device according to claim 16,wherein the semiconductor package is 14×18 mm in outer dimension, andthe semiconductor package is a maximum of 1.46 millimeters in height.32. The storage device according to claim 16, wherein the central regionhas a width about ⅓ of an entire width in a long-side direction of thearray, the signal electrodes and a subset of the dummy electrodes are inthe central region, and the remaining dummy electrodes are spread out inthe outer region in at least one long-side direction from the centralregion.
 33. The storage device according to claim 16, wherein the outerregion is located on both sides of the central region, and the dummyelectrodes are formed in an array to almost occupy at least one of thesides of the outer region.
 34. The storage device according to claim 16,wherein the dummy electrodes are formed in two lines in a short-sidedirection of the array on the outer region, and each of the linesincludes at least three projection-electrodes.
 35. The storage deviceaccording to claim 34, wherein the signal electrodes include Vccelectrodes; the Vcc electrodes are formed in a Vcc electrode line in theshort-side direction, and the Vcc electrode line is next to the twodummy electrode lines.
 36. The storage device according to claim 16,wherein three dummy electrodes are formed in the outer region, and atleast a Vcc electrode in the central region form a line in a long-sidedirection of the array.
 37. The storage device according to claim 16,wherein at least one of the semiconductor chips includes a plurality ofmemory cells, the memory cells being capable of multiple-valuedrecording.
 38. A storage system comprising: a semiconductor packagehaving a plurality of semiconductor chips, a first substrate, a resinencapsulation encapsulating the plurality of semiconductor chips, and anarray of electrodes on a bottom surface of the first substrate; and asecond substrate; wherein the semiconductor package is mounted on thesecond substrate, the electrodes include a plurality of signalelectrodes on a central region of the bottom surface, and a plurality ofdummy electrodes on an outer region outside of the central region, aproportion of a number of the signal electrodes to a total number of theplurality of electrodes is 10-30%, the signal electrodes include a firstpad as a projection-electrode forming pad for a power supply line or asignal line, and a first projection electrode formed on the first pad,and the dummy electrodes include a second pad as a projection-electrodeforming pad for a dummy electrode and a second projection electrodeformed on the second pad.
 39. The storage system according to claim 38,wherein the outer region includes a first region and a second region,the first region including the dummy electrodes surrounding the centralregion and including four corners, the second region including one ormore lines of the dummy electrodes formed outside of the four corners ofthe first region.
 40. The storage system according to claim 38, whereinthe second substrate includes a plurality of conductors, the pluralityof conductors including first conductors and second conductors, thefirst conductors being in contact with the first projection electrodes,the second conductors being in contact with the second projectionelectrodes.
 41. The storage system according to claim 38, wherein atleast one of the dummy electrodes further includes a third pad forburying a vacant region, and no projection-electrode is formed on thethird pad.
 42. The storage system according to claim 38, wherein thecentral region in which the signal electrodes are formed has a widthabout ⅓ to ½ of an entire width of the array.
 43. The storage systemaccording to claim 38, wherein a proportion in number of the signalelectrodes to the electrodes is less than 20%.
 44. The storage systemaccording to claim 38, wherein the signal electrodes are placed toexhibit line symmetry about a center line of the array formed by theelectrodes or point symmetry about a center of the array.
 45. Thestorage system according to claim 38, wherein the dummy electrodes arearrayed to at least one side of an entire circumference of the signalelectrodes.
 46. The storage system according to claim 38, wherein thesemiconductor chips are stacked and encapsulated in the resinencapsulation.
 47. The storage system according to claim 46, wherein aplurality of bonding wires are encapsulated in the resin encapsulation,the bonding wires are electrically connected to the semiconductor chipsand the first substrate, the bonding wires extending from thesemiconductor chips are connected to a wiring pattern at an end of thefirst substrate, and the semiconductor chips are stacked in a slightlydeviating manner in the resin encapsulation.
 48. The storage systemaccording to claim 47, wherein the semiconductor chips are stacked to bedeviated by a predetermined amount such that top surfaces of peripheriesof the semiconductor chips to which the bonding wires are connected arenot overlapped by another one of the semiconductor chips, and one of thebonding wires is connected to one side of each of the semiconductorchips.
 49. The storage system according to claim 38, wherein at leastone of the semiconductor chips has a NAND flash memory incorporatedtherein.
 50. The storage system according to claim 38, furthercomprising a controller mounted on the second substrate, and a powersupply circuit mounted on the second substrate, wherein the plurality ofsemiconductor chips include a first semiconductor chip and a secondsemiconductor chip, the first semiconductor chip and the secondsemiconductor chip are partially overlapped, and a peripheral portion ofthe second semiconductor chip is not overlapped on one side of the firstsemiconductor chip.
 51. The storage system according to claim 38,wherein the semiconductor package is 14×18 mm in outer dimension, andthe semiconductor package is a maximum of 1.46 millimeters in heightfrom the second substrate.
 52. The storage system according to claim 38,wherein the electrodes form a line in a long-side direction of the arrayand a line in a short-side direction of the array, and the electrodesare arrayed in an approximate rectangular shape that has a centermatching that of the first substrate.
 53. The storage system accordingto claim 38, wherein the central region has a width about ⅓ of an entirewidth in a long-side direction of the array, the signal electrodes and asubset of the dummy electrodes are in the central region, and theremaining dummy electrodes are spread out in the outer region in atleast one long-side direction from the central region.
 54. The storagesystem according to claim 38, wherein the outer region is located onboth sides of the central region, and the dummy electrodes are formed inan array to almost occupy at least one of the sides of the outer region.55. The storage system according to claim 38, wherein the dummyelectrodes are formed in two lines in a short-side direction of thearray on the outer region, and each of the lines includes at least threeprojection-electrodes.
 56. The storage system according to claim 55,wherein Vcc electrodes in the central region are formed in a Vccelectrode line in the short-side direction of the array, and the Vccelectrode line is next to the two dummy electrode lines.
 57. The storagesystem according to claim 38, further comprising: bonding pads arrangedon a short side of the first substrate, and through holes in the firstsubstrate that are connected by patterns on the first substrate.
 58. Thestorage system according to claim 38, wherein the first pads areelectrically connected to at least one of the semiconductor chips by athrough hole and a pattern on the first substrate.
 59. The storagesystem according to claim 38, wherein the signal electrodes include aVcc electrode, three dummy electrodes are formed in the outer region,and the Vcc electrode and the three dummy electrodes form a line in along-side direction of the array.
 60. The storage system according toclaim 38, further comprising a controller, wherein the controllercontrols at least one of the semiconductor chips in the semiconductorpackage, the at least one of the semiconductor chips includes a NANDflash memory.
 61. The storage system according to claim 60, furthercomprising a volatile memory mounted on the second substrate.
 62. Thestorage system according to claim 61, wherein the volatile memory isDynamic Random Access Memory.
 63. The storage system according to claim61, wherein a power supply circuit is incorporated in a secondsemiconductor package.
 64. The storage system according to claim 63,wherein an underfill agent is filled between the second substrate andthe second semiconductor package.
 65. The storage system according toclaim 60, further comprising third semiconductor packages mounted on thesecond substrate, the third semiconductor packages including NAND flashmemories.
 66. The storage system according to claim 65, wherein thenumber of the third semiconductor packages is four or more.
 67. Thestorage system according to claim 65, wherein a plurality ofsemiconductor chips are stacked in each of the third semiconductorpackages.
 68. The storage system according to claim 38, wherein aconnector is arranged at an outer periphery of the second substrate. 69.The storage system according to claim 38, wherein at least one of thesemiconductor chips includes a plurality of memory cells, the memorycells being capable of multiple-valued recording.
 70. The storage systemaccording to claim 38, wherein the central region in which the signalelectrodes are formed has a region of a width about ⅓ to ½ of an entirewidth of the array.
 71. The storage system according to claim 38,wherein an outer dimension of the second substrate is substantially thesame in size as that of a 1.8-inch HDD according to the HDD standard.72. A storage system comprising: a mounting substrate; and a pluralityof semiconductor packages mounted on the mounting substrate; wherein atleast one of the semiconductor packages includes: a plurality ofsemiconductor chips; a wiring substrate on which the plurality ofsemiconductor chips are mounted on a first surface; and a plurality ofprojection electrodes formed on a second surface opposite to the firstsurface of the wiring substrate, wherein a plurality ofprojection-electrode forming pads for forming the projection electrodesare arrayed on the second surface, the projection-electrode forming padsinclude first projection-electrode forming pads as projection-electrodeforming pads formed within a central region of the array for at least apower supply line and second projection-electrode forming pads asprojection-electrode forming pads for a dummy electrode formed on anouter region outside of the central region, a proportion of a number ofthe first projection-electrode forming pads in the central region to atotal number of the first and second projection-electrode forming padsis 10-30 percent, the projection electrodes include first projectionelectrodes formed on the first projection-electrode forming pads andsecond projection electrodes formed on the second projection-electrodeforming pads.
 73. The storage system according to claim 72, wherein theouter region includes a first region and a second region, the firstregion including the dummy electrodes surrounding the central region andincluding four corners, the second region including one or more lines ofthe dummy electrodes formed outside of the four corners of the firstregion.
 74. The storage system according to claim 72, wherein themounting substrate includes a plurality of conductors, the plurality ofconductors including first conductors and second conductors, the firstconductors being in contact with the first projection electrodes, thesecond conductors being in contact with the second projectionelectrodes.
 75. The storage system according to claim 72, furthercomprising a power supply circuit mounted on the mounting substrate; anda controller mounted on the mounting substrate, wherein the plurality ofsemiconductor chips include a first semiconductor chip and a secondsemiconductor chip, the first semiconductor chip and the secondsemiconductor chip are partially overlapped, and a peripheral portion ofthe second semiconductor chip is not overlapped on one side of the firstsemiconductor chip, and a bonding pad, to which a bonding wire extendingfrom at least one of the semiconductor chips is connected, is formed atan edge of the first surface of the wiring substrate.
 76. The storagesystem according to claim 72, wherein the central region in which thesignal electrodes are formed has a region of a width about ⅓ to ½ of anentire width of the array.
 77. The storage system according to claim 72,wherein an outer dimension of the mounting substrate is substantiallythe same in size as that of a 1.8-inch HDD according to the HDDstandard.
 78. A storage device comprising: a substrate, and asemiconductor package including a semiconductor chip and an array ofelectrodes on a bottom surface of the semiconductor package, thesemiconductor package being mounted on the substrate, the electrodesincluding a plurality of signal electrodes formed within a centralregion of the bottom surface of the semiconductor package, and aplurality of dummy electrodes formed on an outer region outside of thecentral region, wherein a proportion of a number of the signalelectrodes to a total number of the plurality of electrodes is 10-30percent.
 79. The storage device according to claim 78, wherein thecentral region in which the signal electrodes are formed has a region ofa width about ⅓ to ½ of an entire width of the array.
 80. A storagedevice comprising: a semiconductor package including a semiconductorchip, a substrate, and an array of electrodes on a bottom surface of thesubstrate, the semiconductor package being mounted on the substrate;wherein the electrodes include a plurality of dummy electrodes formed ina rectangular outer region and a plurality of signal electrodes formedwithin a substantially square central region disposed within the outerregion, and the substantially square central region being rotated by 45degrees with respect to the rectangular outer region, the signalelectrodes include a first projection electrode, and the dummyelectrodes include a second projection electrode.
 81. The storage deviceaccording to claim 80, wherein a proportion of a number of the signalelectrodes to a total number of the plurality of electrodes is 10-30%.82. The storage device according to claim 81, wherein a proportion innumber of the signal electrodes to the electrodes is less than 20%. 83.The storage device according to claim 80, wherein the central region inwhich the signal electrodes are formed has a region of a width about ⅓to ½ of an entire width of the array.
 84. A storage device comprising: asubstrate, and a semiconductor package including a semiconductor chipand an array of electrodes on a bottom surface of the semiconductorpackage, the semiconductor package being mounted on the substrate, theelectrodes including a plurality of signal electrodes formed within acentral region of the bottom surface of the semiconductor package, and aplurality of dummy electrodes formed on an outer region outside of thecentral region, wherein the central region in which the signalelectrodes are formed has a region of a width about ⅓ to ½ of an entirewidth of the array.
 85. The storage device according to claim 84,wherein all of the of signal electrodes are formed within the centralregion.